A Framework for Design and Verification of Image Processing Applications using UVM

A simple UVM example with DPI

Designing means to communicate as an SPI master, being a part of AXI interface

Implements a simple UVM based testbench for a simple memory DUT.

A simple UVM testbench using UVM Connect and Octave

This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.

Apply dataclasses concept to testbench automation in Python

A simple testbench with two refmods using UVM Connect

UVM VIP for Single Port RAM Synchronous Read/Write

Language parser

UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

Layered SystemVerilog testbench for verifying a parameterized Synchronous FIFO. Includes directed and constrained-random tests, functional coverage, assertions, and scoreboard-based checking.

A complete UVM-based verification environment for validating YAPP Router functionality using SystemVerilog and Cadence Xcelium, featuring advanced sequences, virtual interfaces, and coverage analysis.

SystemVerilog DV of a RISC-V register file with fault injection and coverage analysis

A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.

Simplified Advanced Encryption Standard (S-AES) Design and Verification Using System Verilog and UVM.

Provides Eclipse plug-ins for developing Accellera PSS

First and Last Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with system verilog + Functional verification.

Verification of Advanced Encryption Standard (AES-128) Using UVM