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Merge pull request #746 from stm32-rs/0.15
Prepare for v0.15.0 release
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‎CHANGELOG.md‎

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## [Unreleased]
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* Use PascalCase for values of enums
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* Added missing TIMx:CR1:OPM, removed unused CNT_H, ARR_H, CCR_H
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* Replace python svd tools with rust alternatives
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* Updated to svd2rust 0.24.0
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* `SVDTOOLS` env value for specifying patching tool
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## [v0.15.0] 2022-07-04
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Common changes:
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* Strip prefixes from many peripheral registers (#661)
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* Add `SVDTOOLS` env value for specifying patching tool (#673)
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* Fix HTML generation on macOS (#679)
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* Replace Python svd tools with Rust alternatives (#701)
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* Added missing TIMx:CR1:OPM, removed unused CNT_H, ARR_H, CCR_H (#684)
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* Use PascalCase for generated values of enums (#727)
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* Updated to svd2rust 0.24.0 (#733)
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* Document RTC ALARM and BKPR (#724)
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* Extensive internal refactor of GPIO patches (#717)
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* Change groupName of ADC_Common to ADC_Common (#719)
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* Fix field access on many SAI fields (#691)
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Family-specific:
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* G0:
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* Clear all vendor provided enumeratedValues
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* Fix DMA and TIM15 register field names
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* G0B1/G0C1: Update SVDs (#666)
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* G0B1/G0C1: Fix previous incorrect deletion of DMA1/2 (#675)
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* Clear all vendor provided enumeratedValues (#686)
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* Update SVDs, document DMA, various other patches (#687)
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* Make FLASH_WRP??R and FLASH_SECR writeable (#690)
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* G070: Rename SYSCFG_VREFBUF to SYSCFG, remove VREFBUF registers (#716)
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* Fix DMA and TIM15 register field names (#695)
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* G4:
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* RCC: Remove RNGSMEN -> RNGEN renaming to have AHB2SMENR.RNGSMEN
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* Fix ADC ADSTP, ADSTART, ADDIS, ADEN bit enumerations (#699)
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* Remove RNGSMEN -> RNGEN renaming to have AHB2SMENR.RNGSMEN (#729)
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* H7:
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* h7b3: clear all enumeratedValues
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* h747: add flash registers mirrored in bank2
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* h747: add midding DSI interrupt (#646)
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* h735, h7b3: remove unavailable DSI peripheral (#648)
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* Make ETH_MAC MMC mask register writable (#658)
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* RM0455: Fix incorrect rename of OCTOSPI peripheral (#653)
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* Arrayify HASH registers (#663)
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* Add bit ranges to HDMI CRC registers (#671)
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* H743/H753: Fix Overdrive and BDMADR fields (#649)
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* h7b3: clear all enumeratedValues (#686)
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* Change DMA CR to only cover SxCR, not LIFCR and HIFCR (#702)
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* H735: Add TIM23 and TIM24 (#712)
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* Fix ADC ADSTP, ADSTART, ADDIS, ADEN bit enumerations (#699)
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* Arrayify HSEM registers (#735, #737)
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* h747: add flash registers mirrored in bank2 (#704)
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* H735: Add CORDIC and FMAC peripherals (#677)
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* H735: Add missing TIM1, DCMI, OTG USB, RNG, LTDC, RAMECC interrupts (#677)
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* Rename DBGSTBD1, DBGSTPD1, DBGSLPD1 fields to match RM (#677)
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* RM0468: Add UART9/USART10, RM0455: fix USART base addresses (#652)
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* F0:
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* F0x1/2/8: Add bit ranges to HDMI CRC registers (#671)
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* Add missing CRC POL register (#710)
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* F2:
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* Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689)
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* Add ADC EXTSEL enumerations (#707)
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* Apply existing OTG_FSv1 fixes (#706)
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* F3:
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* Add missing 'P' to JADST (#696)
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* Fix ADC ADSTP, ADSTART, ADDIS, ADEN bit enumerations (#699)
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* Fix various fields access (#734)
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* F302: Rename `DAC` to `DAC1` (#742)
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* F4:
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* F469: Fix `DSIHSOT_CCR` register name (#664)
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* Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689)
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* Fix OTG_FS registers
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* L4:
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* Added missing channel 2 on TIM15
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* F411: Fix OTG_FS registers (#697)
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* Add ADC EXTSEL enumerations (#707)
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* Add GTPR register to UART (#713)
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* Document TIM2 ITR1_RMP enums (#678)
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* F410/411/412: add BDCR LSEMOD field (#708)
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* F7:
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* Add SDMMC2EN and SDMMC2RST to F765, F7x7, F7x9 (#662)
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* Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689)
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* Add bit ranges to HDMI CRC registers (#671)
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* Add ADC EXTSEL enumerations (#707)
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* Fix ADC DR RDATA name and description (#723)
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* Document safe ranges for CNT/ARR/CCR (#700)
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* Arrayify JPEG memory registers (#725)
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* L0:
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* Re-add TIM21/TIM22 (#659)
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* Fix various fields access (#734)
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* L4:
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* Add documentation for FIREWALL (#660)
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* Arrayify HASH registers (#663)
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* L4R9: Fix `DSIHSOT` interrupt name (#664)
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* L4R9: Add TIM3 and TIM4 (#669)
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* L4x5/6/R9: Rename DBGMCU APB_FZR to remove underscores (#681)
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* Add GPIOx ASCR and BRR registers (#680)
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* Added missing channel 2 on TIM15 (#705)
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* Fix ADC RDATA field name and description. (#723)
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* Add more enums for clock selection registers (#720)
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* Rename `Polynomialcoefficients` field to `POL` (#710)
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* Remove COMP1/COMP2 prefix from field names, document fields (#682)
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* L5:
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* Fix DMA CCR fields, arrayify GTZC VCTR (#715)
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* WB:
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* Arrayify HSEM registers (#735, #737)
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* WL:
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* Put all timers into common TIM group (#657)
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* Fix various fields access (#734)
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* Arrayify HSEM registers (#735, #737)
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Contributors to this release:
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[@LeonSkoog] [@kenbell] [@ryan-summers] [@burrbull] [@richardeoin]
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[@systec-ms] [@DerFetzer] [@newAM] [@jspngh] [@jamwaffles] [@sephamorr]
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[@MathiasKoch] [@omion] [@davidlattimore] [@Sh3Rm4n] [@Windfisch] [@sorki]
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[@taylorh140] [@reitermarkus] [@larchuto] [@jonas-schievink] [@tim-seoss]
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[@Wassasin] [@Gekkio] [@korken89] [@maximeborges] [@sphw] [@dgoodland]
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[@X-yl] [@disasm] [@Pagten] [@oldsheep68] [@TomDeRybel]
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## [v0.14.0] 2021-10-02
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* Fix nvicPrioBits being incorrect in many STM32s (de117ef)
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* Add support for specifying interrupts and modifying CPU node
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[Unreleased]: https://github.com/stm32-rs/stm32-rs/compare/v0.14.0...HEAD
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[Unreleased]: https://github.com/stm32-rs/stm32-rs/compare/v0.15.0...HEAD
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[v0.15.0]: https://github.com/stm32-rs/stm32-rs/compare/v0.14.0...v0.15.0
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[v0.14.0]: https://github.com/stm32-rs/stm32-rs/compare/v0.13.0...v0.14.0
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[v0.13.1]: https://github.com/stm32-rs/stm32-rs/compare/v0.13.0...v0.13.1
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[v0.13.0]: https://github.com/stm32-rs/stm32-rs/compare/v0.12.1...v0.13.0
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[@cyberillithid]: https://github.com/cyberillithid
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[@cyrusmetcalf]: https://github.com/cyrusmetcalf
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[@David-OConnor]: https://github.com/David-OConnor
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[@davidlattimore]: https://github.com/davidlattimore
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[@DerFetzer]: https://github.com/DerFetzer
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[@dgoodland]: https://github.com/dgoodland
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[@diondokter]: https://github.com/diondokter
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[@dirk-dms]: https://github.com/dirk-dms
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[@disasm]: https://github.com/disasm
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[@ehntoo]: https://github.com/ehntoo
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[@eupn]: https://github.com/eupn
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[@Geens]: https://github.com/Geens
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[@Gekkio]: https://github.com/Gekkio
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[@HarkonenBade]: https://github.com/HarkonenBade
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[@helgrind]: https://github.com/helgrind
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[@hnez]: https://github.com/hnez
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[@hoachin]: https://github.com/hoachin
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[@ijager]: https://github.com/ijager
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[@jamwaffles]: https://github.com/jamwaffles
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[@JarLob]: https://github.com/JarLob
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[@jessebraham]: https://github.com/jessebraham
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[@jglauche]: https://github.com/jglauche
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[@jonas-schievink]: https://github.com/jonas-schievink
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[@jordens]: https://github.com/jordens
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[@jorgeig-space]: https://github.com/jorgeig-space
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[@jspngh]: https://github.com/jspngh
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[@karlp]: https://github.com/karlp
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[@kenbell]: https://github.com/kenbell
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[@kevswims]: https://github.com/kevswims
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[@kitzin]: https://github.com/kitzin
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[@korken89]: https://github.com/korken89
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[@larchuto]: https://github.com/larchuto
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[@LeonSkoog]: https://github.com/LeonSkoog
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[@lichtfeind]: https://github.com/lichtfeind
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[@lochsh]: https://github.com/lochsh
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[@lulf]: https://github.com/lulf
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[@lynaghk]: https://github.com/lynaghk
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[@mabezdev]: https://github.com/mabezdev
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[@MarcoIeni]: https://github.com/MarcoIeni
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[@MathiasKoch]: https://github.com/MathiasKoch
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[@mathk]: https://github.com/mathk
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[@matoushybl]: https://github.com/matoushybl]
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[@MattCatz]: https://github.com/MattCatz
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[@noslaver]: https://github.com/noslaver
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[@octronics]: https://github.com/octronics
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[@ofauchon]: https://github.com/ofauchon
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[@oldsheep68]: https://github.com/oldsheep68
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[@omion]: https://github.com/omion
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[@osannolik]: https://github.com/osannolik
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[@Pagten]: https://github.com/Pagten
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[@pawelchcki]: https://github.com/pawelchcki
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[@Piroro-hs]: https://github.com/Piroro-hs
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[@qwandor]: https://github.com/qwandor
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[@ra-kete]: https://github.com/ra-kete
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[@Rahix]: https://github.com/Rahix
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[@reitermarkus]: https://github.com/reitermarkus
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[@rfuest]: https://github.com/rfuest
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[@richard7770]: https://github.com/richard7770
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[@richardeoin]: https://github.com/richardeoin
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[@rmsc]: https://github.com/rmsc
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[@ryan-summers]: https://github.com/ryan-summers
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[@samcrow]: https://github.com/samcrow
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[@sephamorr]: https://github.com/sephamorr
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[@Sh3Rm4n]: https://github.com/Sh3Rm4n
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[@sirhcel]: https://github.com/sirhcel
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[@solderjs]: https://github.com/solderjs
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[@sorki]: https://github.com/sorki
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[@sphw]: https://github.com/sphw
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[@systec-ms]: https://github.com/systec-ms
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[@tachiniererin]: https://github.com/tachiniererin
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[@taylorh140]: https://github.com/taylorh140
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[@therealprof]: https://github.com/therealprof
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[@thinxer]: https://github.com/thinxer
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[@tim-seoss]: https://github.com/tim-seoss
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[@timblakely]: https://github.com/timblakely
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[@timokroeger]: https://github.com/timokroeger
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[@TomDeRybel]: https://github.com/TomDeRybel
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[@torkeldanielsson]: https://github.com/torkeldanielsson
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[@TwoHandz]: https://github.com/TwoHandz
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[@wallacejohn]: https://github.com/wallacejohn
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[@Wassasin]: https://github.com/Wassasin
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[@Windfisch]: https://github.com/Windfisch
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[@X-yl]: https://github.com/X-yl
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[@x37v]: https://github.com/x37v
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[@YruamaLairba]: https://github.com/YruamaLairba
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[@yusefkarim]: https://github.com/yusefkarim

‎README.md‎

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In your own project's `Cargo.toml`:
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```toml
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[dependencies.stm32f4]
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version = "0.14.0"
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version = "0.15.0"
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features = ["stm32f405", "rt"]
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```
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‎scripts/makecrates.py‎

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import re
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import yaml
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VERSION = "0.14.0"
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VERSION = "0.15.0"
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SVD2RUST_VERSION = "0.24.0"
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CRATE_DOC_FEATURES = {

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