This PowerShell script automates the compilation, simulation, and waveform viewing process for Verilog designs using Icarus Verilog and GTKWave. The script allows users to specify a Verilog design file, a testbench file, and perform actions such as compilation, simulation, and waveform visualization.

Run the script using PowerShell with the following syntax:

veri <DesignFile> [Action]

• <DesignFile>: The main Verilog design file (e.g., design.v).
• <Action> (optional): The operation to perform. Defaults to all.
  • compile: Compile the Verilog files.
  • simulate: Run the simulation.
  • view: Open the waveform in GTKWave.
  • all: Perform all steps sequentially (default).

This script currently supports PowerShell. To expand its usability, contributions are welcome for equivalent implementations in:

• Bash (Linux/macOS)
• Batch (Windows CMD)

If you create a Bash or Batch version of this script, feel free to share it!