VHDL implementation of a 16-bit serial-stream mirror detector and data extractor, with external/internal mirror checks and high-speed output.
-
Updated
Dec 5, 2025 - VHDL
VHDL implementation of a 16-bit serial-stream mirror detector and data extractor, with external/internal mirror checks and high-speed output.
Add a description, image, and links to the serial-mirror topic page so that developers can more easily learn about it.
To associate your repository with the serial-mirror topic, visit your repo's landing page and select "manage topics."