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sadrasabourisadrasabouri
committed
update : First stage decoded.
1 parent 9c31184 commit 74e377b

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2 files changed

+98
-39
lines changed

2 files changed

+98
-39
lines changed

‎Hardware/Receiver/Receiver.v‎

Lines changed: 52 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
`include "DeScrambler/DeScrambler.v"
2+
`include "ViterbiDecoder/ViterbiDecoder.v"
23

3-
module Receiver(Input, Reset, Clock, Output, Error);
4+
module Receiver(Input, Reset, Clock, Clock2, Output, Error);
45
/*
56
* Module `Receiver`
67
*
@@ -13,6 +14,7 @@ module Receiver(Input, Reset, Clock, Output, Error);
1314
* Input [1]: Input Wifi frame
1415
* Reset [1]: Active high asynchronous reset
1516
* Clock [1]: Input clock
17+
* Clock2 [1]: Input clock2 (2*Main clock)
1618
* Output [1]: Output data
1719
* Error [1]: Error bit which uses for exception rasing
1820
*
@@ -23,17 +25,22 @@ module Receiver(Input, Reset, Clock, Output, Error);
2325
input wire Input;
2426
input wire Reset;
2527
input wire Clock;
28+
input wire Clock2;
2629

2730
output wire Output;
2831
output reg Error;
2932

3033

3134
parameter MAX_TURNS_PLCP_PREAMBLE = 95; // = 12 * 8 - 1 (12 Symbols, each symbol's a byte)
32-
35+
// Current state register:
36+
reg [3:0] CURRENT_STATE;
37+
3338
reg [0:MAX_TURNS_PLCP_PREAMBLE] Input_buffer;
34-
always @(posedge Clock, posedge Reset) // Save last 96 bit for preambles
39+
wire INPUT_BUFF_CLCK;
40+
assign INPUT_BUFF_CLCK = CURRENT_STATE ? Clock2 : Clock ;
41+
always @(posedge INPUT_BUFF_CLCK, posedge Reset) // Save last 96 bit for preambles
3542
if (Reset)
36-
Input_buffer <= 95'b0;
43+
Input_buffer <= 96'b0;
3744
else
3845
Input_buffer <= {{Input_buffer[1:MAX_TURNS_PLCP_PREAMBLE]}, {Input}};
3946

@@ -73,15 +80,27 @@ module Receiver(Input, Reset, Clock, Output, Error);
7380
end
7481

7582

83+
// ViterbiDecoder Instatiation:
84+
reg viterbi_reset;
85+
wire viterbi_out;
86+
ViterbiDecoder viterbidecoder(
87+
.Input(Input_buffer[94]), // Last input for clock problem
88+
.Reset(viterbi_reset),
89+
.Clock(Clock2),
90+
.Output(viterbi_out)
91+
);
92+
93+
7694
// Wifi-Frame - Parameters:
77-
// Current state register:
78-
reg [3:0] CURRENT_STATE;
7995
// IDLE state:
8096
parameter [3:0] IDLE_STATE = 0;
8197
parameter [0:8*12-1] PREAMBLE_SYMBOLS = {8'hAA, 8'hAA, 8'hAA, 8'hAA,
8298
8'hAA, 8'hAA, 8'hAA, 8'hAA,
8399
8'hAA, 8'hAA, 8'hAA, 8'hAA};
84100

101+
// WAIT4VITERBI:
102+
parameter [3:0] WAIT4VITERBI = 1;
103+
reg [10:1] WAIT4VITERBI_counter;
85104
// Signal state:
86105
// Rate state:
87106
parameter [3:0] SIGNAL_RATE_STATE = 2;
@@ -110,7 +129,7 @@ module Receiver(Input, Reset, Clock, Output, Error);
110129
// PAD_BITS:
111130

112131

113-
always @(posedge Clock, posedge Reset)
132+
always @(posedge INPUT_BUFF_CLCK, posedge Reset)
114133
begin
115134
if (Reset)
116135
begin
@@ -124,26 +143,49 @@ module Receiver(Input, Reset, Clock, Output, Error);
124143
TURNS_SERVICE_STATE <= 4'b0000;
125144
TURNS_PSDU_STATE <= 15'b000_0000_0000_0000;
126145
Error <= 1'b0;
146+
viterbi_reset <= 1'b0;
147+
WAIT4VITERBI_counter <= 10'b0;
127148
end
128149
else
129150
begin
130151
case (CURRENT_STATE)
131152
IDLE_STATE:
132153
begin
133154
descrambler_reset = 1'b0;
155+
$display("%h ?= \n%h", Input_buffer, PREAMBLE_SYMBOLS);
134156
if (Input_buffer == PREAMBLE_SYMBOLS)
157+
begin
158+
CURRENT_STATE <= WAIT4VITERBI;
159+
viterbi_reset <= 1'b1;
160+
$display("New Sequence Found.");
161+
end
162+
end
163+
// ------------------------------------
164+
// Wait for Viterbi Decoder to decode input sequence
165+
// ------------------------------------
166+
WAIT4VITERBI:
167+
begin
168+
viterbi_reset <= 1'b0;
169+
if (WAIT4VITERBI_counter == 0)
170+
$display("Viterbi Reseted.");
171+
WAIT4VITERBI_counter <= WAIT4VITERBI_counter + 10'b00_0000_0001;
172+
if (WAIT4VITERBI_counter == 645)
173+
begin
135174
CURRENT_STATE <= SIGNAL_RATE_STATE;
175+
$display("Here we start to get decoded seq!");
176+
end
136177
end
137178
// ------------------------------------
138179
// PLCP_PREAMBLE::END SIGNAL::START
139180
// ------------------------------------
140181
SIGNAL_RATE_STATE:
141182
begin
142-
RATE[TURNS_RATE_STATE] <= Input;
183+
RATE[TURNS_RATE_STATE] <= viterbi_out;
143184

144185
// Reached to the end of Rate sub-frame
145186
if (TURNS_RATE_STATE == 2'b11)
146187
begin
188+
$display("RATE = %b", RATE);
147189
CURRENT_STATE <= SIGNAL_RESERVERD_STATE;
148190
TURNS_RATE_STATE <= 2'b00;
149191
end
@@ -156,11 +198,12 @@ module Receiver(Input, Reset, Clock, Output, Error);
156198
end
157199
SIGNAL_LENGTH_STATE:
158200
begin
159-
LENGTH[TURNS_LENGTH_STATE] <= Input;
201+
LENGTH[TURNS_LENGTH_STATE] <= viterbi_out;
160202

161203
// Reached to the end of lenght sub-frame
162204
if (TURNS_LENGTH_STATE >= 11) // 12 - 1
163205
begin
206+
$display("LEN = %b", LENGTH);
164207
CURRENT_STATE <= SIGNAL_PARITY_STATE;
165208
TURNS_LENGTH_STATE <= 2'b00;
166209
end

‎Hardware/Receiver/Receiver_tb.v‎

Lines changed: 46 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ module Receiver_tb;
1111
*/
1212
// Inputs
1313
reg Clock;
14+
reg Clock2;
1415
reg Reset;
1516
reg Input;
1617

@@ -22,22 +23,30 @@ module Receiver_tb;
2223
Receiver uut (
2324
.Input(Input),
2425
.Clock(Clock),
26+
.Clock2(Clock2),
2527
.Reset(Reset),
2628
.Output(Output),
2729
.Error(Error)
2830
);
2931

3032
localparam CLK_PERIOD = 0.5;
33+
localparam CLK2_PERIOD = 0.25;
3134

3235
always
3336
begin
3437
Clock = ~Clock;
3538
#CLK_PERIOD;
3639
end
3740

41+
always
42+
begin
43+
Clock2 = ~Clock2;
44+
#CLK2_PERIOD;
45+
end
46+
3847
always
3948
begin
40-
#1;
49+
#0.5;
4150
$display($time, "ns |",
4251
" Reset=%b", Reset,
4352
" Input=%b", Input,
@@ -47,55 +56,62 @@ module Receiver_tb;
4756
end
4857

4958
integer i = 0;
50-
reg [1:288] SEQ_IN = 288'b101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010110100000000100000000000000011101111001001011001000000100010011000101110101101100000110011010100111001111011010000101010111110100101000110111000111111100001110111100101100100100000010001001100;
59+
reg [1:480] SEQ_IN = 480'b101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010111010111001101110110000110111110010110000000000000000001110010111110011101001001011011010101011111000001011110111111111000010001111010011010111000001000101100001001001001010000000110010101100100111100010110001010100111001011011011000100000111110000111101110011010011101000001110111001101101110101000110001100110010101111100111010010001101010111110110101000010111101111111110000100011;
5160

5261
initial
5362
begin
5463
// Initialize Inputs
5564
$display("[START]");
5665
Clock = 0;
66+
Clock2 = 0;
5767
Reset = 0;
58-
Input = SEQ_IN[1];
5968
#10
6069

6170
Reset = 1;
6271
#1;
6372
Reset = 0;
6473

65-
for (i = 2; i <= 288; i = i + 1)
74+
for (i = 1; i <= 96; i = i + 1)
6675
begin
6776
Input = SEQ_IN[i];
6877
#1;
6978
end
70-
end
71-
72-
integer j = 0;
73-
integer N_PASS = 0;
74-
reg [1:4] DESIRED_OUT = 4'b1001;
75-
initial
76-
begin
77-
#10;
78-
#1;
7979

80-
#141;
81-
$display("[DATA::START]");
82-
for (j = 1; j <= 4; j = j + 1)
80+
// Coded Section:
81+
for (i = 97; i <= 480; i = i + 1)
8382
begin
84-
if (Output == DESIRED_OUT[j])
85-
begin
86-
$display("[OK] (", j, "/", 4, ")");
87-
N_PASS = N_PASS + 1;
88-
end
89-
else
90-
$display("[FAILED] (", j, "/", 4, ") Expected:%b | Got:%b", DESIRED_OUT[j], Output);
91-
#1;
83+
Input = SEQ_IN[i];
84+
#0.5;
9285
end
86+
end
9387

94-
if (N_PASS == 4)
95-
$display("ALL TEST PASSED. :)");
96-
else
97-
$display(4 - N_PASS, " test(s) failed. :(");
88+
// integer j = 0;
89+
// integer N_PASS = 0;
90+
// reg [1:4] DESIRED_OUT = 4'b1001;
91+
// initial
92+
// begin
93+
// #10;
94+
// #1;
9895

99-
$display("[DATA::END]");
100-
end
96+
// #141;
97+
// $display("[DATA::START]");
98+
// for (j = 1; j <= 4; j = j + 1)
99+
// begin
100+
// if (Output == DESIRED_OUT[j])
101+
// begin
102+
// $display("[OK] (", j, "/", 4, ")");
103+
// N_PASS = N_PASS + 1;
104+
// end
105+
// else
106+
// $display("[FAILED] (", j, "/", 4, ") Expected:%b | Got:%b", DESIRED_OUT[j], Output);
107+
// #1;
108+
// end
109+
110+
// if (N_PASS == 4)
111+
// $display("ALL TEST PASSED. :)");
112+
// else
113+
// $display(4 - N_PASS, " test(s) failed. :(");
114+
115+
// $display("[DATA::END]");
116+
// end
101117
endmodule

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